Trenched mosfets with embedded schottky in the same cell

ABSTRACT

A semiconductor power device includes trenched semiconductor power device comprising a trenched gate surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a substrate. The semiconductor power device further includes an insulation layer covering the trenched semiconductor power device with a source-body contact trench opened therethrough the source and body regions and extending into an epitaxial layer below the body regions and filled with contact metal plug therein. The semiconductor power device further includes an embedded Schottky diode disposed near a bottom of the source-body contact trench below the contact metal plug wherein the Schottky diode further includes a Schottky barrier layer having a barrier height for reducing a leakage current through the embedded Schottky diode during a reverse bias between the drain and the source.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to the cell structure, deviceconfiguration and fabrication process of power semiconductor devices.More particularly, this invention relates to a novel and improved cellconfiguration and processes to manufacture MOSFET device with embeddedSchottky diodes in the same cell such that integrated cells with spacingsavings and lower capacitance and higher performance are achieved.

2. Description of the Related Art

Conventional technologies for high efficiency DC/DC applications, aSchottky diode is usually added externally in parallel to asemiconductor power device, e.g., a power MOSFET device. FIG. 1A is acircuit diagram that illustrates the implementation of a Schottky with apower MOSFET device. The Schottky diode (SKY) is connected in parallelto the MOSFET device with a parasitic PN body diode to function as aclamping diode to prevent the body diode from turning on. In order toachieve higher speed and efficiency, once the parasitic P/N diode isturned on, both the electron and hole carriers are generated and thatwould require longer time to eliminate the carriers by electron-holecombination while the Schottky Diode is single carrier, i.e., electroncarrier only and that can be drawn simply by the drain Electrode. Therequirement for the clamping effect is that the Forward Voltage of theSchottky diode Vf is less than the parasitic PN diode (˜0.7V). As theelectronic devices become more miniaturized, there are requirement tointegrate the Schottky diode as part of the semiconductor power deviceas an IC chip to reduce the space occupied by the Schottky diode insteadof connecting the Schottky diode as an external electronic component.

FIG. 1B is a cross sectional view of a trenched MOSFET device integratedwith trench Schottky diodes as that disclosed by U.S. Pat. No.6,351,018. The configuration as disclosed in the patented invention hasa disadvantage that the Schottky diodes occupy additional space that isabout the same space as the MOSFET. The trench Schottky diodes furthersuffer from a high leakage between the drain and source due to theincrease in the phosphorus dopant concentration in the channel regionduring the sacrificial and gate oxidation processes. Furthermore, thedevice as shown has a higher capacitance due to the presence of thetrench MOS-Schottky structure which has inherent parasitic capacitancefrom trench sidewall and bottom in trench MOS-Schottky as shown in leftside of the cross section view in FIG. 1B.

In U.S. Pat. No. 6,433,396, a trench MOSFET device with a planarSchottky diode is disclosed as that shown in FIG. 1C. The configurationagain has an advantage that the planar Schottky diode occupiesadditional space. Also, the formation process requires additionalcontact mask for the Schottky diode thus increases the cost andprocesses complications for producing the MOSFET power device withSchottky diode.

In U.S. Pat. No. 6,998,678 discloses another trench semiconductorarrangement as shown in FIG. 1D with a MOS transistor which has a gateelectrode, arranged in a trench running in the vertical direction of asemiconductor body, and a Schottky diode which is connected in parallelwith a drain-source path (D-S) and is formed by a Schottky contactbetween a source electrode and the semiconductor body. Again, theconfiguration has the same disadvantage that the Schottky diodes occupyadditional space thus limiting the further miniaturization of thedevice. Furthermore, the manufacturing cost is increased due to therequirement that an additional P+ mask is required to form the Schottkydiodes.

Therefore, there is still a need in the art of the semiconductor devicefabrication, particularly for design and fabrication of the trenchedpower device, to provide a novel cell structure, device configurationand fabrication process that would resolve these difficulties and designlimitations. Specifically, it is desirable to provide more integratedsemiconductor power devices with embedded Schottky diode that canaccomplish space saving and capacitance reduction such that the abovediscussed technical limitations can be resolved.

SUMMARY OF THE PRESENT INVENTION

It is therefore an aspect of the present invention to provide new andimproved semiconductor power device configuration and manufactureprocesses for providing semiconductor power devices with embeddedSchottky diode such that space occupied by separate Schottky diodes canbe saved and one of the major technical limitations discussed above canbe overcome.

Another aspect of the present invention is to provide new and improvedsemiconductor power device configuration and manufacture processes forproviding semiconductor power devices with embedded Schottky diode inthe same cell such that parasitic capacitance can be reduced and deviceperformance can be improved.

Another aspect of the present invention is to provide new and improvedsemiconductor power device configuration and manufacture processes forproviding semiconductor power devices with embedded Schottky diode inthe same cell wherein the manufacturing processes can be simplified withreduced number of masks required such that the production costs can bereduced and reliability of the products can be enhanced.

Another aspect of the present invention is to provide new and improvedsemiconductor power device configuration and manufacture processes forproviding semiconductor power devices with embedded Schottky diode inthe same cell wherein a dopant regions is provided at the bottom of acontact trench below the Schottky layer to reduce the forward voltage ofthe Schottky diodes such that improved device performance is achieved.

Another aspect of the present invention is to provide new and improvedsemiconductor power device configuration and manufacture processes forproviding semiconductor power devices with embedded Schottky diode inthe same cell wherein a dopant regions is provided at the bottom of acontact trench below the Schottky layer to reduce the ldsx is reducedand device performance improvements are achieved.

Briefly, in a preferred embodiment, the present invention discloses asemiconductor power device comprising trenched semiconductor powerdevice comprising a trenched gate surrounded by a source regionencompassed in a body region above a drain region disposed on a bottomsurface of a substrate. The semiconductor power device further includesan insulation layer covering the trenched semiconductor power devicewith a source-body contact trench opened therethrough and furtherthrough the body regions into an epitaxial layer underneath and filledwith contact metal plug therein. The semiconductor power device furtherincludes an embedded Schottky diode disposed near a bottom of thesource-body contact trench below the contact metal plug wherein theSchottky diode further includes a Schottky barrier layer having abarrier height for reducing a leakage current through the embeddedSchottky diode during a reverse bias between the drain and the source.In an exemplary embodiment, the semiconductor power device furtherincludes a contact enhancement dopant region disposed along a sidewallof the source-body contact trench for improving an electrical contact ofthe contact metal plug to the source and body regions. In an exemplaryembodiment, the embedded Schottky diode further includes a CoSi2/TiNbarrier layer disposed below the contact metal plug. In an exemplaryembodiment, the metal contact plug further includes a tungsten plugfilling in the source-body contact trench for contacting the bodyregions. In an exemplary embodiment, the a contact enhancement dopantregion disposed along a side wall of the source-body contact trenchfurther includes a P-type body-dopant region for improving an electricalcontact of the contact metal plug to the body regions. In an exemplaryembodiment, the embedded Schottky diode further includes a PtSi barrierlayer disposed below the contact metal plug. In an exemplary embodiment,the embedded Schottky diode further includes a barrier layer having abarrier height larger than a leakage prevention voltage for preventing aleakage current during a reverse bias between the drain and the sourceand the barrier layer having a forward voltage drop less than aparasitic body diode between the body region and an epitaxial layersurrounding the body region. In an exemplary embodiment, the contactmetal plug further includes a Ti/TiN barrier layer surrounding atungsten core as a source-body contact metal. In an exemplaryembodiment, the semiconductor power device further includes a thinresistance-reduction conductive layer disposed on a top surface coveringthe insulation layer and contacting the contact metal plug whereby theresistance-reduction conductive layer having a greater area than a topsurface of the contact metal plug for reducing a source-body resistance.In an exemplary embodiment, the semiconductor power device furtherincludes a thin resistance-reduction conductive layer includes a Ti orTi/TiN layer disposed on a top surface covering the insulation layer andcontacting the contact metal plug whereby the resistance-reductionconductive layer having a greater area than a top surface of the contactmetal plug for reducing a source-body resistance. In an exemplaryembodiment, the semiconductor power device further includes a thickfront metal layer disposed on top of the resistance-reduction layer forproviding a make contact with layer for a wire or wireless bondingpackage. In an exemplary embodiment, the semiconductor power devicefurther includes a trenched MOSFET device. In an exemplary embodiment,the semiconductor power device further includes a source-dopant regiondisposed below the source-body contact trench in contact with thebarrier layer of the Schottky diode having a dopant concentration of N2with N2>N1 where N1 is a dopant concentration of an epitaxial layersurrounding the body region supported on the semiconductor substrate. Inan exemplary embodiment, the semiconductor power device further includesa source-dopant region disposed below the source-body contact trench incontact with the barrier layer of the Schottky diode having a dopantconcentration of N2 with N2<N1 to reduce a Drain-Source leakage currentat a reverse bias where N1 is a dopant concentration of an epitaxiallayer surrounding the body region supported on the semiconductorsubstrate. In an exemplary embodiment, the trenched gate is filled witha dielectric material padded by a gate oxide layer with a bottom gateoxide layer significantly thicker than the gate oxide layer disposedalong sidewalls of the trenched gate.

These and other objects and advantages of the present invention will nodoubt become obvious to those of ordinary skill in the art after havingread the following detailed description of the preferred embodiment,which is illustrated in the various drawing figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A to 1D are circuit diagram and cross sectional views of MOSFETpower devices of related disclosures of conventional deviceconfigurations implemented with various Schottky diode integrations.

FIGS. 2 to 7 are cross sectional views for showing the semiconductorpower devices with embedded Schottky diodes in the same cell disposed onthe source/body contact trenches as various exemplary embodiments ofthis inventions.

FIGS. 8A to 8G are a serial of side cross sectional views for showingthe processing steps for fabricating a MOSFET device as shown in FIGS. 2and 4 of this invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Please refer to FIG. 2 shows a side cross-sectional view of a trenchMOSFET 100 with embedded Schottky in the same cell of this invention.The trenched MOSFET 100 is supported on a substrate 105 formed with anepitaxial layer 110. The MOSFET device 100 includes trenched gates 120disposed in a trench with a gate insulation layer 115 formed over thewalls of the trench. A body region 125 that is doped with a dopant ofsecond conductivity type, e.g., P-type dopant, extends between thetrenched gates 120. The P-body regions 125 encompassing a source region130 doped with the dopant of first conductivity, e.g., N+ dopant. Thesource regions 130 are formed near the top surface of the epitaxiallayer surrounding the trenched gates 120. The trench MOSFET deviceincludes an embedded Schottky formed near the bottom of the trenchcontact filled with a tungsten plug 155. The Schottky diodes are formedin the contact trench with a CoSi2/TiN layer 145 and a barrier layer 150underneath the trench contact 155. In order to improve the source/bodycontact, a P+ dopant region 140 is formed along the sidewall to haveimproved ohmic contact between the trench contact 155 and the P-bodyregions 125. The MOSFET device with the embedded Schottky diodes iscovered with a low resistance layer composed of Ti or Ti/TiN that has alarge contact area to the tungsten trench contact 155 and extending overthe oxide insulation layer 135 on top of the trench gates 120. A metallayer 165 composed of aluminum alloy covering the device is patternedinto gate pad and source/body contacts (not specifically shown). Asshown in FIG. 2, the Schottky barrier layer 145 form the embeddedSchottky diodes near the bottom or the trench contact with a parallelparasitic diode formed between the body region 125 and the N-epitaxiallayer 110. The barrier layer 145 can be CoSi2, TiSi2 and PtSi, which hasbarrier height larger than 0.5V, resulting in low leakage current in theembedded Schottky diode during reverse bias between drain and sourcewhile providing lower Vf (forward voltage drop) at forward bias than theparasitic body diode between P-body 125 and N epi layer 110. The forwardvoltage drop Vf and the reverse leakage current Idsx can be optimized bythe critical dimension (CD) of the trench contact and depth, and thebarrier layer 145.

The MOSFET device with embedded Schottky diodes have the advantages thatthe Schottky diodes are provided with less space occupied by theSchottky diodes because the diodes are formed as part of the trenchcontacts in the same area as part of the cells of the MOSFET powerdevice. Compared to the patented inventions disclosed above, the spacesaving is at least 50%. The source contact with either N+ or P+ regions,i.e., dopant regions 140 are formed on the sidewalls of the trenchcontact and the Schottky diodes formed on the bottom of the trenchcontact achieve process savings because there is no requirement of P+mask when compared with the device as that disclosed in U.S. Pat. No.6,998,678. Furthermore, since the MOSFET and the Schottky diodes sharethe same trenches, there is less parasitic capacitance thus providingdevices capable of providing higher performance with higher switchingspeed.

Beside optimizing trench contact CD and depth, and the Schottky barrierlayer 145 to target Vf, there is another alternative method to furtherimprove Vf by ion implantation of 1^(st) conductivity dopant into trenchbottom. FIG. 3 is another exemplary embodiment of a MOSFET 100-1 with anembedded Schottky in the same cell with an N dopant region 170 having adopant concentration of N2 where N2>N1 and N1 is the dopantconcentration of the epitaxial layer 105. The N-dopant region 170 isprovided to lower the Vf of the Schottky diode because the Vf is lowerwith a higher doping concentration N2 contacting to the Schottky barrierlayer 145.

FIG. 4 is another exemplary embodiment of a MOSFET 100-2 with a purposeto reduce the Drain-Source leakage current at reverse bias. The MOSFET100-2 has an embedded Schottky in the same cell with an N dopant region170′ having a dopant concentration of N2 where N2<N1 and N1 is thedopant concentration of the epitaxial layer 105. The N-dopant region17′0 is provided to have a lower ldsx because the N2 is in contact withthe Schottky barrier that has lower doping concentration than the epilayer 110. The Schottky contact between the barrier layer and siliconhas a lower Vf when the silicon has high doping concentration, and alower leakage current Idsx between Drain-Source when the silicon has lowdoping concentration. There is trade-off between the Vf and the Idsx.When the leakage current is too high, the leakage current will consumemore power at an off-state, which becomes very undesirable forapplications in portable system such as cell phone, notebook usingbattery.

FIG. 5 is another exemplary embodiment of a MOSFET 100-2 with anembedded Schottky in the same cell with a thicker oxide layer 115′ atbottom of the trench gate 120. The thicker oxide layer at the bottom ofthe trench gate 120 which is thinner than gate oxide along trenchsidewall, is provided to have a reduce gate-drain capacitance. The thickoxide at trench bottom sandwiched between trench gate and drain has lesscapacitance than the single gate oxide along trench sidewall becauseCgd, i.e., the capacitance between gate and drain, has a reverseproportional relationship with the gate oxide thickness.

FIG. 6 is another exemplary embodiment of a MOSFET 100-4 with anembedded Schottky in the same cell with an N dopant region 170 having adopant concentration of N2 where N2>N1 and N1 is the dopantconcentration of the epitaxial layer 105. The N-dopant region 170 isprovided to lower the Vf of the Schottky diode because lower Schottkybarrier height is achieved with the N2 layer. The barrier height ofSchottky is function of doping concentration and the barrier layermaterial. A lower doping concentration leads to a lower Schottky barrierheight that results in a lower Vf but higher Idsx. Meanwhile, there is atrade-off between Vf and Idsx. However, the benefit of the N2 is toreduce Vf without degrading the Drain to Source breakdown voltage as aresult of same epitaxial doping concentration. Furthermore, the MOSFET100-4 has a thicker oxide layer 115′ at bottom of the trench gate 120.The thicker oxide layer at the bottom of the trench gate 120 is providedto have a reduce gate-drain capacitance.

FIG. 7 is another exemplary embodiment of a MOSFET 100-5 with anembedded Schottky in the same cell with an N dopant region 170′ having adopant concentration of N2 where N2<N1 and N1 is the dopantconcentration of the epitaxial layer 105. The N-dopant region 17′0 isprovided to have a lower ldsx because N2 has lower doping concentrationcausing higher Schottky barrier height. Furthermore, the MOSFET 100-5has a thicker oxide layer 115′ at bottom of the trench gate 120. Thethicker oxide layer at the bottom of the trench gate 120 is provided tohave a reduce gate-drain capacitance.

Referring to FIGS. 8A to 8F for a serial of side cross sectional viewsto illustrate the fabrication steps of a MOSFET device as that shown inFIGS. 2, 3, and 4. In FIG. 4A, a trench mask (not shown) is applied toopen a plurality of trenches in an epitaxial layer 210 supported on asubstrate 205 by employing a dry silicon etch process. An oxidationprocess is then performed to form an oxide layer covering the trenchwalls. The trench is oxidized with a sacrificial oxide to remove theplasma damaged silicon layer during the process of opening the trench.Then an oxide layer 215 is grown followed by depositing a polysiliconlayer 220 to fill the trench and covering the top surface and then dopedwith an N+ dopant. The polysilicon layer 220 filling the trenches areeither etched back or removed by applying a chemical mechanicalplanarization process (CMP) to remove the polysilicon above the topsurface. In FIG. 8B, the manufacturing process proceeds by implanting aP-body implant with a P-type dopant. Then an elevated temperature isapplied to diffuse the P-body 225 into the epitaxial layer 210. Then aN+ source dopant implant is carried out to form the source regions 230followed by applying an elevated temperature to diffuse the sourceregions 230 further into the body region 225. An oxide deposition isthen carried out to form a thick oxide layer 235 covering over the topsurface of the device. In FIG. 8C, a dry contact oxide etch is carriedout with a contact etch mask (not show) to open trenches 237 through theoxide layer 235 into the body regions 225 between the trenched gates220. Then a boron angle ion implantation is carried out to form P+region 240 along the sidewalls of the contact trenches 237. In FIG. 8D,a contact silicon etch is performed to open the trenches 237 deeperthrough the body region 225 and further into Epi layer 210.

In FIG. 8E, a layer 245 of Co/TiN is deposited followed by a rapidthermal anneal process to form a CoSi2 250 thus forming a Schottkybarrier layer. Then the tungsten contact plug 255 is deposited into thecontact trench followed by a W/Co/TiN etch back to remove the W/Co/TiNlayer from above the contact trenches 225. Then a Ti or TiN lowresistance layer 260 is deposited over the top surface followed bydepositing an aluminum alloy layer 265 as a metal contact layer. A metalpatterning process is performed (not shown) to complete themanufacturing process of the device. FIG. 8F showing an implant processfor implanting As ions to form the dopant region 170 with dopantconcentration N2>N1 or implanting Boron or BF2 ions for the dopantregion 170′ N2<1 after completing the process of FIG. 8D and the processshown in FIG. 8G is the same as that described in FIG. 8E after theimplanting process completed in FIG. 8F.

According to the above drawings and descriptions, this invention furtherdiscloses a method for method for manufacturing a trenched semiconductorpower device includes a step of forming said semiconductor power devicewith a trenched gate surrounded by a source region encompassed in a bodyregion above a drain region disposed on a bottom surface of a substrate.The method further includes the steps of covering the MOSFET cell withan insulation layer and applying a contact mask for opening asource-body contact trench extending through the source and body regionsinto an epitaxial layer underneath for filling a contact metal plugtherein. And, the method further includes a step of forming an embeddedSchottky diode by forming a Schottky barrier layer near a bottom of thesource-body contact trench below the contact metal plug with theSchottky barrier layer having a barrier height for reducing a leakagecurrent through the embedded Schottky diode during a reverse biasbetween the drain and the source. In an exemplary embodiment, the methodfurther includes a step of forming a contact enhancement dopant regionalong a sidewall of the source-body contact trench for improving anelectrical contact of the contact metal plug to the source and bodyregions. In an exemplary embodiment, the step of forming the embeddedSchottky diode further includes a step of forming a CoSi2/TiN barrierlayer at a bottom surface of the source-body contact trench. In anexemplary embodiment, the step of forming the embedded Schottky diodefurther includes a step of forming a PtSi barrier layer at a bottomsurface of the source-body contact trench. In an exemplary embodiment,the method further includes a step of forming a source-dopant regionbelow the source-body contact trench in contact with the barrier layerof the Schottky diode having a dopant concentration of N2 with N2>N1where N1 is a dopant concentration of an epitaxial layer surrounding thebody region supported on the semiconductor substrate. In an exemplaryembodiment, the method further includes a step of forming asource-dopant region below the source-body contact trench in contactwith the barrier layer of the Schottky diode having a dopantconcentration of N2 with N2<N1 to reduce a Drain-Source leakage currentat a reverse bias where N1 is a dopant concentration of an epitaxiallayer surrounding the body region supported on the semiconductorsubstrate. In an exemplary embodiment, the method further includes astep of forming a gate insulation layer padded on sidewalls and a bottomsurface of the trenched gate and filling the trenched gate with adielectric material by with the gate insulation layer on the bottomsurface of the trenched gate significantly thicker than the gateinsulation layer disposed along sidewalls of the trenched gate.

Although the present invention has been described in terms of thepresently preferred embodiment, it is to be understood that suchdisclosure is not to be interpreted as limiting. Various alternationsand modifications will no doubt become apparent to those skilled in theart after reading the above disclosure. Accordingly, it is intended thatthe appended claims be interpreted as covering all alternations andmodifications as fall within the true spirit and scope of the invention.

1. A trenched semiconductor power device comprising a trenched gatesurrounded by a source region encompassed in a body region above a drainregion disposed on a bottom surface of a substrate, wherein saidsemiconductor power device further comprising: an insulation layercovering said trenched semiconductor power device with a source-bodycontact trench opened therethrough and further extending through saidbody region into an epitaxial region underneath and filled with contactmetal plug therein; and an embedded Schottky diode disposed near abottom of said source-body contact trench below said contact metal plugwherein said Schottky diode further comprising a Schottky barrier layerdirectly contacting an epitaxial layer below a bottom of said contacttrench thus forming a vertical Schottky diode along a source-draindirection having a barrier height for reducing a leakage current throughsaid embedded Schottky diode during a reverse bias between said drainand said source.
 2. The trenched semiconductor power device of claim 1further comprising: a contact enhancement dopant region disposed alongsidewalls of said source-body contact trench for improving an electricalcontact of said contact metal plug and to said body regions.
 3. Thetrenched semiconductor power device of claim 1 wherein: said embeddedSchottky diode further comprising a CoSi2/TiN barrier layer disposedbelow said contact metal plug directly contacting said epitaxial layerbelow said contact trench.
 4. The trenched semiconductor power device ofclaim 1 wherein: said metal contact plug further comprising a tungstenplug filling in said source-body contact trench for contacting saidsource and body regions and said vertical Schottky diode disposed belowsaid tungsten plug.
 5. The trenched semiconductor power device of claim2 wherein: said a contact enhancement dopant region disposed alongsidewalls of said source-body contact trench further comprising a P-typebody-dopant region having a higher dopant concentration than said bodyregion for improving an electrical contact of said contact metal plug tosaid body regions.
 6. The trenched semiconductor power device of claim 1wherein: said embedded Schottky diode further comprising a PtSi barrierlayer disposed below said contact metal plug directly contacting saidepitaxial layer below said contact trench.
 7. The trenched semiconductorpower device of claim 1 wherein: said embedded Schottky diode furthercomprising a barrier layer having a barrier height larger than 0.5V forreducing a leakage current during a reverse bias between said drain andsaid source and said barrier layer having a forward voltage drop lessthan a parasitic body diode between said body region and said epitaxiallayer surrounding and below said body region.
 8. The trenchedsemiconductor power device of claim 1 wherein: the contact metal plugfurther comprising a Ti/TiN barrier layer surrounding a tungsten core asa source-body contact metal.
 9. The trenched semiconductor power deviceof claim 1 further comprising: a thin resistance-reduction conductivelayer disposed on a top surface covering said insulation layer andcontacting said contact metal plug whereby said resistance-reductionconductive layer having a greater area than a top surface of saidcontact metal plug for reducing a source-body resistance.
 10. Thetrenched semiconductor power device of claim 1 further comprising: athin resistance-reduction conductive layer comprising a Ti or Ti/TiNlayer disposed on a top surface covering said insulation layer andcontacting said contact metal plug whereby said resistance-reductionconductive layer having a greater area than a top surface of saidcontact metal plug for reducing a source-body resistance.
 11. Thetrenched semiconductor power device of claim 10 further comprising: athick front metal layer disposed on top of said resistance-reductionlayer for providing a contact layer for a wire or wireless bondingpackage.
 12. The trenched semiconductor power device of claim 1 wherein:said trenched semiconductor power device further comprising a trenchedMOSFET device.
 13. The trenched semiconductor power device of claim 1further comprising: a source-dopant region disposed below saidsource-body contact trench in direct contact with said barrier layer ofsaid Schottky diode having a dopant concentration of N2 with N2>N1 whereN1 is a dopant concentration of said epitaxial layer surrounding andbelow said body region supported on said semiconductor substrate. 14.The trenched semiconductor power device of claim 1 further comprising: asource-dopant region disposed below said source-body contact trench indirect contact with said barrier layer of said Schottky diode having adopant concentration of N2 with N2<N1 to reduce a Drain-Source leakagecurrent at a reverse bias where N1 is a dopant concentration of saidepitaxial layer surrounding and below said body region supported on saidsemiconductor substrate.
 15. The trenched semiconductor power device ofclaim 1 wherein: said trenched gate is filled with a dielectric materialpadded by a gate oxide layer with a bottom gate oxide layersignificantly thicker than said gate oxide layer disposed alongsidewalls of said trenched gate.
 16. The trenched semiconductor powerdevice of claim 1 further comprising: a source-dopant region disposedbelow said source-body contact trench in contact with said barrier layerof said Schottky diode having a dopant concentration of N2 with N2>N1where N1 is a dopant concentration of said epitaxial layer surroundingand below said body region supported on said semiconductor substrate;and said trenched gate is filled with a dielectric material padded by agate oxide layer with a bottom gate oxide layer significantly thickerthan said gate oxide layer disposed along sidewalls of said trenchedgate.
 17. The trenched semiconductor power device of claim 1 furthercomprising: a source-dopant region disposed below said source-bodycontact trench in contact with said barrier layer of said Schottky diodehaving a dopant concentration of N2 with N2<N1 to reduce a Drain-Sourceleakage current at a reverse bias where N1 is a dopant concentration ofsaid epitaxial layer surrounding and below said body region supported onsaid semiconductor substrate; and said trenched gate is filled with adielectric material padded by a gate oxide layer with a bottom gateoxide layer significantly thicker than said gate oxide layer disposedalong sidewalls of said trenched gate.
 18. A method for manufacturing atrenched semiconductor power device comprising a step of forming saidsemiconductor power device with a trenched gate surrounded by a sourceregion encompassed in a body region above a drain region disposed on abottom surface of a substrate, the method further comprising: coveringsaid MOSFET cell with an insulation layer and applying a contact maskfor opening a source-body contact trench extending through said sourceand body regions and into an epitaxial layer below said body region forfilling a contact metal plug therein; and forming an embedded Schottkydiode by forming a Schottky barrier layer near a bottom of saidsource-body contact trench below said contact metal plug with saidSchottky barrier layer having a barrier height for reducing a leakagecurrent through said embedded Schottky diode during a reverse biasbetween said drain and said source.
 19. The method of claim 18 furthercomprising a step of: forming a contact enhancement dopant region alonga side wall of said source-body contact trench for improving anelectrical contact of said contact metal plug to said body regions. 20.The method of claim 18 wherein: said step of forming said embeddedSchottky diode further comprising a step of forming a CoSi2/ TiN barrierlayer at a bottom surface of said source-body contact trench.
 21. Themethod of claim 18 of claim 1 wherein: said step of forming saidembedded Schottky diode further comprising a step of forming a PtSibarrier layer at a bottom surface of said source-body contact trench.22. The method of claim 18 further comprising: forming a source-dopantregion below said source-body contact trench in contact with saidbarrier layer of said Schottky diode having a dopant concentration of N2with N2>N1 where N1 is a dopant concentration of an epitaxial layersurrounding said body region supported on said semiconductor substrate.23. The method of claim 18 further comprising: forming a source-dopantregion below said source-body contact trench in contact with saidbarrier layer of said Schottky diode having a dopant concentration of N2with N2<N1 to reduce a Drain-Source leakage current at a reverse biaswhere N1 is a dopant concentration of an epitaxial layer surroundingsaid body region supported on said semiconductor substrate.
 24. Themethod of claim 18 further comprising: forming a source-dopant regionbelow said source-body contact trench in contact with said barrier layerof said Schottky diode having a dopant concentration of N2 with N2>N1where N1 is a dopant concentration of an epitaxial layer surroundingsaid body region supported on said semiconductor substrate; and forminga gate insulation layer padded on sidewalls and a bottom surface of saidtrenched gate and filling said trenched gate with a dielectric materialby with said gate insulation layer on said b&tom surface of saidtrenched gate significantly thicker than said gate insulation layerdisposed along sidewalls of said trenched gate.
 25. The method of claim18 further comprising: forming a gate insulation layer padded onsidewalls and a bottom surface of said trenched gate and filling saidtrenched gate with a dielectric material by with said gate insulationlayer on said bottom surface of said trenched gate significantly thickerthan said gate insulation layer disposed along sidewalls of saidtrenched gate.
 26. The method of claim 18 further comprising: forming asource-dopant region below said source-body contact trench in contactwith said barrier layer of said Schottky diode having a dopantconcentration of N2 with N2<N1 to reduce a Drain-Source leakage currentat a reverse bias where N1 is a dopant concentration of an epitaxiallayer surrounding said body region supported on said semiconductorsubstrate; and forming a gate insulation layer padded on sidewalls and abottom surface of said trenched gate and filling said trenched gate witha dielectric material by with said gate insulation layer on said bottomsurface of said trenched gate significantly thicker than said gateinsulation layer disposed along sidewalls of said trenched gate.